1. Field of the Invention
The present invention relates to methods of etching trenches in silicon, and more particularly to methods of etching trenches in silicon while maintaining good photoresist selectivity.
2. Brief Description of the Background Art
A number of semiconductor devices, including optical waveguides, optical switches and MOSFET (metal oxide semiconductor field effect transistor) devices require the formation of silicon trenches at some point in their fabrication. Depending on the application, trench depths typically range from 1 to 4 microns in width and 0.5 to 5 in depth, although depths and widths beyond these ranges are clearly possible. In order to etch such silicon trenches, either a photoresist mask or an oxide hard-mask is typically used.
The use of an oxide hard-mask in the process integration sequence is presently preferred, because silicon etching at high etch rates, along with high selectivity relative to the oxide mask, is readily achieved using halogen-based chemistry (CF4, Cl2, SF6, etc.) with oxygen addition. For instance, with SF6/O2 chemistry, high etch rates, for example  greater than 1 micron/min (i.e.,  greater than 10,000 Angstroms/min), can be achieved, along with very high silicon:mask selectivity, for example,  greater than 20:1. In addition, the process produces low levels of chamber deposits, allowing high mean wafers between cleans (MWBC) values to be achieved. However, in producing the hard mask, a layer of the hard mask material (typically an oxide) is first provided, followed by the application of a resist mask, after which the hard mask material is etched through apertures in the resist mask. As a result, relative to processes in which trenches are directly defined with a photoresist mask, an additional oxide-etching step is required to define the mask, and the associated cost is undesirable for low cost (and hence low margin) and high volume devices.
Defining trenches with a photoresist mask simplifies the integration sequence and allows sidewall taper to be controlled. However, traditional silicon/polysilicon etch chemistry is typically based on HBr/Cl2 chemistry, which has its own limitations. For example, the etch rates with HBr/Cl2 chemistry are limited to only about 3000 xc3x85/min or less, limiting process throughput. Moreover, the silicon:resist selectivity with this chemistry has an upper limit of about 2.5:1. Finally, this chemistry produces significant chamber deposition.
Other chemistries are known, such as SF6/HBr/O2 chemistry and SF6/CFH3/O2 chemistry, which have somewhat better etch rates (about 1 micron/min) and comparable silicon:resist selectivities (about 2-3:1), but produce trenches with rough sidewalls.
The present invention is directed to improved methods for forming a trench within a silicon substrate. According to one embodiment of the invention, a masked substrate is initially provided that comprises (a) a silicon substrate and (b) a patterned resist layer over the silicon substrate. The patterned resist layer has one or more apertures formed therein. Subsequently, a trench is formed in the substrate through the apertures in the resist layer by an inductive plasma-etching step, which is conducted using plasma source gases that comprise SF6 and at least one fluorocarbon gas. Preferred pressures for this process range from 5-70 mT, more preferably 10-20 mT. Preferred fluorocarbon gases are CHF3, CH2F2 and C4F8, with CHF3 being more preferred. Preferred SF6:CHF3 volume ratios range from 1:1 to 1:10, more preferably from 1:3 to 1:8. Preferably, N2 is added to the source gases of the above process. Preferred (SF6+CHF3):N2 volume ratios preferably range from 1:3 to 5:1, more preferably from 1:2 to 2:1.
According to a further embodiment of the present invention, Cl2 is added to the source gases of the above process. Preferred amounts of Cl2 range from 1 to 80% of the volume of SF6 present in the source gases, more preferably from 5 to 40%. With the addition of Cl2, the taper of the trench sidewalls can be varied, for example, to between 88 to 89 degrees in taper.
The processes of the present invention are capable of providing etching rates that range, for example, from 0.5 to 2 microns per minute and silicon:resist selectivities ranging, for example, from 3:1 to 6:1.
One advantage of the present invention is that silicon trenches can be formed at high etch rates relative to traditional HBr/Cl2 chemistry, leading to significant improvements in process throughput.
Another advantage of the present invention is that silicon trenches can be formed with high silicon:resist selectivity relative to traditional HBr/Cl2 chemistry.
Another advantage of the present invention is that trenches can be formed with good profile control.
Yet another advantage of the present invention is that chamber deposits are reduced relative to traditional HBr/Cl2 chemistry, due to the fluorine-based chemistry of the present invention. Hence, MWBC values are increased.
The above and other embodiments and advantages of the present invention will become immediately apparent to those of ordinary skill in the art upon reading the detailed description and claims to follow.